Published: December 6, 2022
Updated: April 8, 2025

Regarding semiconductor miniaturization, I talked about Moore’s Law and miniaturization, which is a major trend in semiconductor industry, in Vol. 1, and semiconductor processes and lithography, which is a key process for semiconductor miniaturization, in Vol. 2. In this volume, I would like to talk about how miniaturization has progressed.

Table of Contents

Semiconductor Miniaturization and Process Name
International Technology Roadmap for Semiconductors (ITRS)
Example of Roadmap - Lithography -

Volume 3: Semiconductor Miniaturization and International Technology Roadmap

Semiconductor Miniaturization and Process Name

Semiconductor processes are referred to by their dimensions, for example, as 0.18 µm process. In this case, 0.18 µm is generally (or customarily) the smallest dimension in the process which represents the line width of the part of the transistor called the gate electrode (at least we thought so). The next generation after 0.18 µm is 0.13 µm. Since 0.13 ÷ 0.18 = 0.72, it is reduced by a factor of about 0.7. In terms of area, since it is 0.7 x 0.7 = 0.49, which is about half, the density of the element doubles after one generation. Semiconductor processes have repeatedly progressed in this manner to the next generation (shrinking to about 0.7 times the size of the previous generation) in about two to three years. To give an actual example, 0.5 µm → 0.35 µm → 0.25 µm → 0.18 µm → 0.13 µm → 90 nm → 65 nm, etc. (1990s to 2000s).

Note: µm and nm: µm (micrometer) is 10^-6 meter or one millionth meter, nm (nanometer) is 10^-9 meter or one billionth meter, e.g. 0.18 µm = 180 nm

As mentioned above, an old process names almost represented the smallest dimension of that process (the line width of the gate electrode of the transistor). As far as I have experienced, this was generally correct up to 65 nm. The reason I wrote “generally” is that the smallest dimension of the 65 nm process was 60 nm, for example, and there were some such differences. After that (I have not actually experienced the next generation after 65 nm, i.e., after 45 nm, so this is just what I have heard), however, it seems that it has become increasingly difficult to simply make transistors smaller with the same trend without changing the structure of transistors. Although various technologies have been introduced to overcome these difficulties, the most advanced transistors have a three-dimensional (3D) structure because the conventional planar (2D) structure of the transistor can no longer maintain the trend.

The most advanced processes (7nm, 5nm, or 3nm), as of early 2025, using the latest 3D transistor structures and the latest EUV lithography technology appear to have gate electrode line width (gate length) of at least 10nm. There is a huge gap between the process name and the reality. If someone tells this to an engineer who was actively involved in process development in the 1990s, I think many of them will be surprised. They will say, “I wonder what the numbers in process names are all about.”

From the late 2010s to around 2020, news emerged that Intel, which had been leading the miniaturization race, was struggling with then cutting-edge processes, such as 10 nm and 7 nm. At the time, TSMC and Samsung had mass-produced 7 nm and were about to start mass-producing 5nm, so Intel seemed to be lagging. However, according to Intel, its 10 nm process was equivalent to other companies’ 7 nm processes. After reviewing various analyses and information available online, I also concluded that Intel’s 10 nm was comparable to other companies’ 7 nm. This example illustrates that for the most advanced semiconductor processes, simply comparing the numerical values in process names has become meaningless.

Subsequently, Intel has changed the naming of its processes. What was previously called “10nm Enhanced SuperFin” has been renamed “Intel 7.” It seems to indicate that it is comparable to other companies’ 7 nm processes. TSMC and Samsung have also removed the “nm” designation from their process names. For example, as of early 2025, the most advanced mass-production process, formerly referred to as 3 nm, is now called N3 by TSMC, Intel 3 by Intel, and SF3 by Samsung (although in many cases, the previous designation is still listed alongside). However, the numbers in these names do not directly correspond to the actual dimensions of device patterns. Therefore, even if the numbers are the same, it does not mean that these processes are equivalent. In the end, the only way to understand is to look at the details.

Note: Since the scope of my experience is processes for general logic products and analog mixed logic products, the above discussion is also based on that. In reality, each product area, such as processors and memories, has different requirements, and each process evolves in its own way. In processes for processors, the gate length seems to be finer than that of general processes for logic products even in the same process generation.

International Technology Roadmap for Semiconductors (ITRS)

Miniaturization has been progressing in the manner described in the previous section to realize Moore’s Law, and a technology roadmap that concretely indicated this progress was created. The first roadmap was the 1992 edition of the NTRS (National Technology Roadmap for Semiconductors) created by the SIA (Semiconductor Industry Association). Since the 1998 edition, an international roadmap called the ITRS (International Technology Roadmap for Semiconductors) had been created with the participation of industry associations in Europe, Japan, Korea, and Taiwan. While fully revised editions had been published in odd years and partially revised editions in even years, the 2015 edition was the last.

What roles did the roadmap play? Developing semiconductor miniaturization cannot be carried out by semiconductor device makers alone. Since manufacturing equipment and various materials are made by equipment and material makers, cooperation among respective device, manufacturing equipment, and material makers is essential. It would also be impractical to develop completely different equipment and materials for each device maker. As the whole industry, including makers of devices, equipment, and materials, they must be aligned to some extent in common aspects, and the roadmap may have been meaningful.

In fact, in the ITRS it is described that “In the last three decades, the growing size of the required investments has motivated industry collaboration and spawned many R&D partnerships, consortia, and other cooperative ventures. To help guide these R&D programs,” it was initiated. (ITRS 2011 Edition Executive Summary, page 1). It is also described that “Thus, the Roadmap has been put together in the spirit of a challenge—essentially, “What technical capabilities need to be developed for the industry to stay on Moore’s Law and the other trends?” (ITRS 2011 Edition Executive Summary, page 1), we can see that it was created based on maintaining Moore’s Law.

The ITRS provided a roadmap for the next 15 years to maintain Moore’s Law. Since it is now more likely that miniaturization will reach a standstill within that time frame, the 2015 version was prepared and published as “ITRS 2.0” under a new policy that takes semiconductor application areas as the starting point for discussion, rather than the traditional ITRS to achieve the realization of Moore’s Law. The 2015 edition of ITRS 2.0 was, however, the first and final version, and was succeeded by a new activity, the International Roadmap for Devices and Systems (IRDS), which has a broader scope.

The ITRS report can be viewed and downloaded on the Semiconductor Industry Association (SIA) website by searching for “ITRS,” as of January 2025. Similar reports from IRDS, the successor to ITRS, can be viewed and downloaded on the IRDS website on the roadmap page.

Note: The discrepancy between process names and reality, as mentioned in the previous section, is also discussed in the Executive Summary of the IRDS reports. For example, refer to Section 1.2.2 (page 24) in the 2023 edition.

Example of Roadmap - Lithography -

Since I talked about lithography in the last volume, here is an example of a roadmap for lithography from the ITRS 2013 edition.

(ITRS 2013 Edition Lithography, page 6)

The roadmap covers a 15-year period, up to 2028. The area circled in red describes candidate exposure technologies for the future. The top one, 193 nm DP, is a technology in mass production and means ArF excimer laser 193 nm double patterning. Under that are some candidate exposure technologies for further miniaturization. The more the miniaturization of the process, the more the candidates there are. The “QP” is a kind of multi-patterning and an abbreviation for quadruple patterning. Among the lithography technology candidates listed in the 2013 roadmap, the one that was commercialized after ArF excimer laser (193nm) DP and QP was EUV. Since the late 2010s, EUV has been applied to the mass production of cutting-edge logic semiconductor products. Among the other candidates, the one that is closest to practical implementation as of early 2025, to the best of my knowledge, is imprint. Canon released a mass-production system in 2023. It is reported that Kioxia is conducting verification aimed at applying it to mass production of flash memory. This lithography technology is called nanoimprint lithography (NIL). As for the other technologies, ML2 and DSA, as far as I know, they have not yet reached practical implementation for mass production in the most advanced semiconductor processes. The “ML2” is an abbreviation for maskless lithography, which means direct writing by an electron beam, and the “DSA” is an abbreviation for directed self-assembly.

Note: The word “imprint” means “to stamp” or “press a mark.” Nanoimprint lithography (NIL) is a technology that makes fine patterns not by using light to transfer patterns, but literally by pressing a stamp-like mold onto the substrate. Compared to EUV lithography, which requires massive, expensive, and power-consuming equipment, NIL is a simpler, less expensive, and more energy-efficient technology. Canon, Kioxia, and DNP are jointly developing this technology.

Note: Direct writing by an electron beam: This technology draws circuit patterns directly on a wafer surface covered with an electron-sensitive material by an electron beam instead of transferring circuit patterns on masks. It has been researched and developed since the 1970s. The limitations of lithography using light were sometimes called out in the late 1970s and around 1980, and the direct writing by an electron beam was considered as a promising alternative technology. In fact, when I was new to the job (early 1980s), I was assigned to consider the introduction of this technology. Although it was not used in the wafer process due to low throughput for mass production and the progress of optical exposure technology, it is used for making circuit pattern on masks.

Since the previous volume, I have discussed the technical aspects related to miniaturization, and in the next volumes, I would like to talk a little more about business aspects.

On April 8, 2025, the following updates were made:
1. In the section “Semiconductor Miniaturization and Process Name,” the third paragraph and following were revised.
2. In the “International Semiconductor Technology Roadmap (ITRS),” the final paragraph was revised. URL links also updated.
3. In the section “Example of Roadmap -Lithography-,” the latter part was revised to reflect technological developments since the blog was published.

Click below to read this series.

Semiconductor Miniaturization:
Volume 1: Semiconductor Miniaturization: What is Moore’s Law?
Volume 2: Semiconductor Miniaturization and Manufacturing Process
Volume 3: Semiconductor Miniaturization and International Technology Roadmap
Volume 4: Semiconductor Miniaturization and Semiconductor Business
Volume 5: Semiconductor Miniaturization and Semiconductor Business (Part 2)
Volume 6: Semiconductor Miniaturization and Semiconductor Devices
Volume 7: Semiconductor Miniaturization: What is MOSFET Scaling?
Volume 8: Semiconductor Miniaturization: Limitations of MOSFET Scaling
Volume 9: Semiconductor Miniaturization and Analog Circuits

Shift to Larger Diameter Silicon Wafers:
Volume 10: Shift to Larger Diameter Silicon Wafers: How a Common Material, Silicon, Became a Main Player