Regarding semiconductor miniaturization, I talked about Moore's Law and miniaturization, which is a major trend in semiconductor industry, in Vol. 1, and semiconductor processes and lithography, which is a key process for semiconductor miniaturization, in Vol. 2. In this volume, I would like to talk about how miniaturization has progressed.
Click below to read past articles,
Volume 1 Semiconductor Miniaturization: What Is Moore's Law?
Volume 2 Semiconductor Miniaturization And Manufacturing Process
Volume 3 Semiconductor Miniaturization and International Technology Roadmap for Semiconductors
Semiconductor Miniaturization and Process Name
Semiconductor processes are referred to by their dimensions, for example, as 0.18 µm process. In this case, 0.18 µm is generally (or customarily) the smallest dimension in the process which represents the line width of the part of the transistor called the gate electrode (at least we thought so). The next generation after 0.18 µm is 0.13 µm. Since 0.13 ÷ 0.18 = 0.72, it is reduced by a factor of about 0.7. In terms of area, since it is 0.7 x 0.7 = 0.49, which is about half, the density of the element doubles after one generation. Semiconductor processes have repeatedly progressed in this manner to the next generation (shrinking to about 0.7 times the size of the previous generation) in about two to three years. To give an actual example, 0.5 µm → 0.35 µm → 0.25 µm → 0.18 µm → 0.13 µm → 90 nm → 65 nm, etc. (1990s to 2000s).
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* µm and nm: µm (micrometer) is 10-6 meter or one millionth meter, nm (nanometer) is 10-9 meter or one billionth meter, e.g. 0.18 µm = 180 nm
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As mentioned above, an old process names almost represented the smallest dimension of that process (the line width of the gate electrode of the transistor). As far as I have experienced, this was generally correct up to 65 nm. The reason I wrote "generally" is that the smallest dimension of the 65 nm process was 60 nm, for example, and there were some such differences. After that (I have not actually experienced the next generation after 65 nm, i.e., after 45 nm, so this is just what I have heard), however, it seems that it has become increasingly difficult to simply make transistors smaller with the same trend without changing the structure of transistors. Although various technologies have been introduced to overcome these difficulties, the most advanced transistors have a three-dimensional (3D) structure because the conventional planar (2D) structure of the transistor can no longer maintain the trend.
The line width of the gate electrode in the 7 nm and 5 nm processes that employ transistors with cutting-edge three-dimensional structures is more than 10nm. There is a huge gap between the process name and the reality. If someone tells this to an engineer who was actively involved in process development in the 1990s, I think many of them will be surprised. They will say, “I wonder what the numbers in process names are all about.”
In recent years, there has been news about Intel, which should have been leading the miniaturization race, but is now struggling with cutting-edge 10 nm and 7 nm processes. Since TSMC and Samsung have mass-produced 7 nm and started mass-producing 5 nm, it seems that Intel is lagging, but according to Intel, Intel's 10 nm is equivalent to other companies' 7 nm, and various information and analysis that can be gathered on the Internet seem to indicate that Intel's 10 nm is indeed equivalent to other companies' 7 nm. With leading-edge processes, a simple comparison of just the numbers in these process names is no longer meaningful.
| * Since the scope of my experience is processes for general logic products and analog mixed logic products, the above discussion is also based on that. In reality, each product area, such as processors and memories, has different requirements, and each process evolves in its own way. In processes for processors, the gate length seems to be finer than that of general processes for logic products even in the same process generation. |
International Technology Roadmap for Semiconductors (ITRS)
Miniaturization has been progressing in the manner described in the previous section to realize Moore's Law, and a technology roadmap that concretely indicated this progress was created. The first roadmap was the 1992 edition of the NTRS (National Technology Roadmap for Semiconductors) created by the SIA (Semiconductor Industry Association). Since the 1998 edition, an international roadmap called the ITRS (International Technology Roadmap for Semiconductors) had been created with the participation of industry associations in Europe, Japan, Korea, and Taiwan. While fully revised editions had been published in odd years and partially revised editions in even years, the 2015 edition was the last.
What roles did the roadmap play? Developing semiconductor miniaturization cannot be carried out by semiconductor device makers alone. Since manufacturing equipment and various materials are made by equipment and material makers, cooperation among respective device, manufacturing equipment, and material makers is essential. It would also be impractical to develop completely different equipment and materials for each device maker. As the whole industry, including makers of devices, equipment, and materials, they must be aligned to some extent in common aspects, and the roadmap may have been meaningful.
In fact, in the ITRS it is described that "In the last three decades, the growing size of the required investments has motivated industry collaboration and spawned many R&D partnerships, consortia, and other cooperative ventures. To help guide these R&D programs," it was initiated. (ITRS 2011 Edition Executive Summary, page 1). It is also described that "Thus, the Roadmap has been put together in the spirit of a challenge—essentially, “What technical capabilities need to be developed for the industry to stay on Moore’s Law and the other trends?” (ITRS 2011 Edition Executive Summary, page 1), we can see that it was created based on maintaining Moore's Law.
The ITRS provided a roadmap for the next 15 years to maintain Moore's Law. Since it is now more likely that miniaturization will reach a standstill within that time frame, the 2015 version was prepared and published as "ITRS 2.0" under a new policy that takes semiconductor application areas as the starting point for discussion, rather than the traditional ITRS to achieve the realization of Moore's Law. The 2015 edition of ITRS 2.0 was, however, the first and final version, and was succeeded by a new activity, the International Roadmap for Devices and Systems (IRDS), which has a broader scope.
The ITRS report can be viewed and downloaded from the ITRS Web site at ITRS REPORT (http://www.itrs2.net/itrs-reports.html).
Example of Roadmap - Lithography -
Since I talked about lithography in the last volume, here is an example of a roadmap for lithography from the ITRS 2013 edition.
(ITRS 2013 Edition Lithography, page 6)
The roadmap covers a 15-year period, up to 2028. The area circled in red describes candidate exposure technologies for the future. The top one, 193 nm DP, is a technology in mass production and means ArF excimer laser 193 nm double patterning. Under that are some candidate exposure technologies for further miniaturization. The more the miniaturization of the process, the more the candidates there are. The "QP" is a kind of multi-patterning and an abbreviation for quadruple patterning. There are several other candidates besides EUV, but they have not been put into practical use as of the end of 2020. The "ML2" is an abbreviation for maskless lithography, which means direct writing by an electron beam, and the "DSA" is an abbreviation for directed self-assembly.
| *Direct writing by an electron beam: This technology draws circuit patterns directly on a wafer surface covered with an electron-sensitive material by an electron beam instead of transferring circuit patterns on masks. It has been researched and developed since the 1970s. The limitations of lithography using light were sometimes called out in the late 1970s and around 1980, and the direct writing by an electron beam was considered as a promising alternative technology. In fact, when I was new to the job (early 1980s), I was assigned to consider the introduction of this technology. Although it was not used in the wafer process due to low throughput for mass production and the progress of optical exposure technology, it is used for making circuit pattern on masks. |
Since the previous volume, I have discussed the technical aspects related to miniaturization, and in the next volumes, I would like to talk a little more about business aspects.
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